Semiconductor chips continue to have a monumental impact upon our society, and are presently used in devices ranging from computers to telephones to automobiles and the like. Indeed, any modern device that performs any type of computing, control, electronic sensing, communications or the like typically includes at least several controllers, memories, processors or other integrated logic circuits implemented on a semiconductor chip. Many conventional semiconductor chips now include thousands, millions or even more transistors capable of completing complex data processing tasks in fractions of seconds.
As semiconductor chips and their associated manufacturing techniques become increasingly complex, however, the need arises for enhanced testing techniques. In recent years, so-called “design for test” (DFT) practices that incorporate testing mechanisms into the design of a chip have become prevalent in the semiconductor industry. IEEE Standard 1149.1 (commonly called the “JTAG” standard after the Joint Test Action Group that originally formulated the standard), for example, describes a widely-implemented hardware specification that can be used to test interconnectivity between chips operating on a common circuit board. Chips built in accordance with the JTAG standard include a test access port (TAP) for placing signals onto chip interface pins via boundary shift registers (BSRs) that serially connect each pin on the chip to the TAP. By applying proper signals to the TAPs associated with various chips on a circuit board, engineers can perform debugging and diagnostic tests to isolate and correct manufacturing defects such as unconnected pins, missing devices, incorrectly placed or rotated devices, or the like.
While JTAG is intended primarily as a system-level test, other DFT constructs provide testing for logic contained within the chip itself. “Built-in self test” (BIST) modules and/or “automatic test pattern generation” (ATPG) features, for example, are becoming increasingly prevalent. Conventional BIST and ATPG typically exploit chains of interconnected storage elements (e.g. flip flops, latches, etc.) within the chip to serially process applied test data. The results of the test for each chain are then compared against known results to identify faults occurring within the chain, and in logic between the chains. While these techniques can be effective in identifying internal faults within the chip, their usefulness can be limited in practice, particularly with regard to tests that call for a system logic isolation wrapper, which can be cumbersome to implement using conventional testing circuitry.
As a result, it is desirable to formulate a technique for effectively testing the logic contained within a semiconductor chip without significantly increasing the amount of circuitry present on the chip. In addition, it is desirable to expand currently-available BSR capabilities to extend testability control in various environments. Furthermore, other desirable features and characteristics of the present invention will become apparent from the subsequent detailed description and the appended claims, taken in conjunction with the accompanying drawings and the foregoing technical field and background.